`timescale 1ns / 1ps
//Name: Robert Smith
//PID: A08609119
//Name: Shreenidhi Chowkwale
//PID: A09089080

// D_WIDTH  : data width
// PA_WIDTH : port (i.e. IO channel) address width
 
module core#(parameter D_WIDTH = 34, PA_WIDTH = 4, A_WIDTH = 10, I_WIDTH = 17, FIFO_WIDTH = 68)
(
    input  clk,
    input  reset_i,
    
    // I/O interface
    input  [D_WIDTH-1 : 0]  in_data_i,
    input  in_ack_i,
    input  out_ack_i,
    output in_req_o,
    output out_req_o,
    output [PA_WIDTH-1 : 0] in_addr_o,
    output [PA_WIDTH-1 : 0] out_addr_o,
    output [D_WIDTH-1 : 0]  out_data_o,
	 
	 //Timing test outputs
	 output [D_WIDTH - 1 : 0] rd0_o,
	 output [D_WIDTH - 1 : 0] rd1_o,
	 output [D_WIDTH - 1 : 0] wd_o
);



wire dequeue;
wire restart;
wire [A_WIDTH - 1 : 0] restart_addr;
wire load_store_valid;
wire store_en;
wire [A_WIDTH - 1 : 0] load_store_addr;
wire [I_WIDTH - 1 : 0] store_data;
wire [FIFO_WIDTH - 1 : 0] load_data;
wire load_data_valid;
wire [FIFO_WIDTH - 1 : 0] instruction_data;
wire [A_WIDTH - 1 : 0 ] instruction_addr;
wire instruction_valid;

fetch fetch_unit 
	(
		.clk(clk)
		,.dequeue_i(dequeue)
		,.restart_i(restart)
		,.restart_addr_i(restart_addr)
		,.load_store_valid_i(load_store_valid)
		,.store_en_i(store_en)
		,.load_store_addr_i(load_store_addr)
		,.store_data_i(store_data)
		,.load_data_o(load_data)
		,.load_data_valid_o(load_data_valid)
		,.instruction_data_o(instruction_data)
		,.instruction_addr_o(instruction_addr)
		,.instruction_valid_o(instruction_valid)
	);
	
wire [I_WIDTH - 1 : 0] instruction_data_backend = instruction_data[FIFO_WIDTH - 1 : FIFO_WIDTH - 17];
wire [A_WIDTH - 1 : 0] instruction_label = instruction_data[FIFO_WIDTH - 25 : FIFO_WIDTH - 34];
wire [D_WIDTH - 1 : 0] instruction_imm = instruction_data[FIFO_WIDTH - 35 : 0];

backend backend_unit
	(
		.clk(clk)
		,.reset_i(reset_i)
		,.instruction_data_i(instruction_data_backend)
		,.instruction_label_i(instruction_label)
		,.instruction_imm_i(instruction_imm)
		,.instruction_addr_i(instruction_addr)
		,.instruction_valid_i(instruction_valid)
		,.load_data_i(load_data)
		,.dequeue_o(dequeue)
		,.restart_o(restart)
		,.restart_addr_o(restart_addr)
		,.load_store_valid_o(load_store_valid)
		,.store_en_o(store_en)
		,.load_store_addr_o(load_store_addr)
		,.store_data_o(store_data)
		,.in_req_o(in_req_o)
		,.out_req_o(out_req_o)
		,.in_addr_o(in_addr_o)
		,.out_addr_o(out_addr_o)
		,.in_data_i(in_data_i)
		,.out_data_o(out_data_o)
		,.in_ack_i(in_ack_i)
		,.out_ack_i(out_ack_i)
		,.rd0_o(rd0_o)
		,.rd1_o(rd1_o)
		,.wd_o(wd_o)
	);
endmodule
